Study And Realization of High Performance Reconfigurable Processor Architecture for Mission Critical Digital Signal Processing Applications

Abstract

Recent developments in space technology and reconfigurable architecture such as Field Programmable Gate Arrays (FPGAs) have generated the need to revisit hardware and software architecture of satellite on-board-processing applications for Digital Signal Processing (DSP). In view of that, mission critical applications require features such as 1) bug fix and system update, 2) fault tolerance, 3) online fault tolerance, 4) online diagnosis and repair, 5) system reusability, 6) performance improvement, and 7) security. Recent generation FPGAs offer features such as reconfiguration, reprogram-ability, and especially dynamic reconfiguration, including runtime reconfiguration. Although, these developments in FPGA technology allow realization of afore mentioned flexible approach to design and update, a unified generic scalable architecture that comprehensively addresses each one of afore mentioned needs is required for the next generation mission critical applications using FPGAs. The Reconfigurable Processor Architecture Mission-critical for DSP (Re-PAM DSP) proposed as part of this research work is a generic platform which can be super posed on existing combinatorial or sequential digital system, and does not require knowledge of system functionality or encryption algorithm. In this study, reconfiguration is achieved by three steps- static reconfiguration, quasi static reconfiguration and dynamic reconfiguration. Mission critical systems are susceptible to Single Event Upset (SEU) effect in radiation environment. The thesis introduces generic platform for Single Event Upset (SEU) monitoring system that addresses 1) bug fix and system update, 2) fault tolerance, 3) online fault tolerance, 4) online diagnosis and repair, and 5) system reusability. Recent publications rely on scrubbing methods to handle SEU, but persistent SEU handling needs close to 200% area and power resource using variations of Triple Modular Redundancy (TMR). An innovative Multiple Bit Upsets (MBU) handling method using parallel detect and scrubbing on multiple functional units is proposed, that has only 1-2% power, 1% spare CLB and 7-8% mitigation control logic overhead, with no throughput reduction but 1us-10ms of single fault recovery time. Historical data has been published for testpads using shift-registers, small combinational circuits and memory arrays, but current research compares the results using a testpad that is more realistic and comprehensive with Arithmetic Logic Unit (ALU), multiplier, counters and shifters, Multiply-And-Accumulate (MAC), coprocessors and even multiprocessor SOC. Thus, an innovative dynamic reconfiguration method is used in the testpad platform to generate a truly interlocking self healing system to be deployed in space to address aforementioned items - 5) system reusability, and 6) performance improvement for mission critical satellite on-board-processing applications. As technology races towards custom design for mission critical applications, two trends collide. The first is to lower cost for low volume custom design through use of FPGA with reconfigurable design, while the second raises stakes of compromised security in mission-critical applications to devastating impact. These trends are giving rise to another field- to provide combination of reliability and security in FPGA applications under the framework of Reliability and Security Engines (RSE). A novel architecture is proposed to countermeasure the side channel attacks on cryptographic algorithms to address (item 7) Security in FPGA applications. The proposed architecture helps randomize power consumption of SoC irrespective of the data values and their cryptographic algorithms. The architecture utilizes hardware modules of random size and power to be active randomly at run time. The proposed reconfigurable platform based architecture has succeeded in integrating piece meal solutions for fault tolerance, reliability and security features into a very robust and compelling architecture that is a) scalable with application size b) independent of target application or encryption algorithm c) portable across platforms that support partial reconfiguration, and also d) modular, by proposing numerous knobs for each feature to trade off the resources against SEU occurrence environment and mission critical security needs of the application.