CIC Filter Implementation on FPGA

Abstract

A class of digital linear phase finite impulse response (F1R) fillers for decimal it m (sampling rate dcecrease) and interpolation (sampling rate increase) are presented. They require no multipliers and use limited storage making them an economical alternative to conventional implementations for certain applications A digital filter in this class consists of cascaded ideal integrator stages operating at a high sampling rate and an equal number of comb stages Operating at a low sampling rate and an equal number of comb stages operating at a low sampling rate. Together, a single integrator-comb pair produces a uniform FIR, The number of cascaded integrator comb pans is chosen to meet design requirements for aliasing of Imaging error. Design procedures are given for both decimation and interpolation filter's with the emphasis on frequency response and register width A new architecture for the implementation of high-order decimation filter is described here. The C'lC filler has proved to be an effective element in high declination or interpolation systems. The architecture includes carry-save implementation of the recursive integrator stages. comb stages and a programmable counter for the programmable decimator (21 to 2") J. which produces selectable power-of-two output clocks. This produces a high-speed operation, reduces the required chip area, decreases the critical path, and reduces the power dissipation. The project also includes ripple carry architecture for Decimator & Interpolator with good results. The simulation results of my design are exactly same with coregen CIC results. The project also includes the hardware realization of the CIC filler on Field Programmable Logic Array. Furthermore, to improve the filter's pass band response, combination of cascaded-integrated-comb (CIC) multirate filter structure with filter sharpening techniques can be done. This allows the first-stage CIC decimation filter to be followed by a fixed-coefficient filter in place of programmable-coefficient filter- rather than a programmable filter, thereby achieving a significant hardware reduction over existing approaches. Moreover, the use of fixed -coefficient filters improve the overall system throughput rate.