Implementation of Hardware Simulator in FPGA for X-Ray Dectection Payload

Abstract

Simulation is the one of the most useful techniques to test the functionality of module. This report includes design and implementation of the simulator that is used to test the module of “CHANDRAYAN-I” project. Due to the prohibitively high cost of CZT detector modules, they can not be used in the payload till the payload circuits are fully developed. To overcome this difficulty, hardware simulator for X-Ray detection payload system has been developed. I understood the system and decided what to simulate and what should be the input and output of the system. Because this is a hardware simulator, I have designed different modules for the simulator. Three signals need to be generated. These signals are 10 bit data sample value, 12 bit address and an EOC signal. The data and address have Gaussian distribution. Prime focus is to generate Gaussian random numbers in hardware. For that Gaussian Random Number generation algorithm, similar to Box-Muller algorithm, has been designed for this application. Results of original algorithm and modified algorithm are included. This result shows that modified algorithm is better than original algorithm for this application. Simulator has been implemented in VHDL using XILINX ISE 6. Different modules have been implemented to implement entire design. VHDL code, schematic diagram and simulations of modules are included here. After implementation of individual units all units have been integrated. Integration of all these units is the simulator that I had to develop. Code, schematic and simulation of the entire system (Integration) are also included. Area analysis of individual units and the entire system is included. Implementation of Hardware Simulator in FPGA for X-Ray Detection Payload