Simulation for Process Development and Circuit Design of FLASH EEPROM in 0.8um Technology

Abstract

years, and further growth in the near future is foreseen, especially for Flash memories (in which a single cell can be electrically programmable and a large number of cells called a block, sector, or page are electrically erasable at the same time) due to their enhanced flexibility against electrically programmable read-only memories, which are electrically programmable but erasable via ultraviolet exposure. Electrically erasable and programmable read-only memories, which are electrically erasable and programmable per single byte, will be manufactured for specific applications only, since they use larger areas and, therefore, are more expensive. This is a conservative scenario, since there might be changes due to technology evolution. On the other hand, the realization of new generations of Flash memories that can be erased by blocks of different sizes, emulating EEPROM’s in some applications, and with single power supply widens the field of applicability for Flash memories and encourages new uses. There are two major applications for Flash memories; one application is the possibility of nonvolatile memory integration in logic systems. The other application is to create storing elements, like memory boards or solid-state hard disks. Semiconductor Memories are an essential part of any design. They requirement may vary from few flip-flops to kilobytes. There are various kinds of semiconductor memories available such as mask ROM, EEPROM, Flash Memory, Static Ram, DRAM etc. Each has different features and is employed according to the specific requirements of the system. There have been tremendous improvements in the architecture and layout strategies of memories as they form the densest circuits and are considered to occupy largest area in the system. This thesis deals with the study of design of FLASH EEPROM and its implementation with the 0.8-micron process in CMOS technology. This was undertaken in the VLSI: R&D DESIGN department of Semiconductor Complex Ltd. At Mohali (Punjab). This thesis deal with the study of process development and the design of the Flash EEPROM which includes the pre silicon parameter extraction, SPICE modeling of Flash cell and then circuit designing of some blocks of the FLASH EEPROM memory. In this I have done following things Study of different memories Study of the cell structure of Flash memory and how cell is read, programmed and erase. Detail study of the Process requirement of the flash cell Study of various Physical phenomena used to programmed and erase the cell Study architecture of the Flash memory Process simulation and Device simulation of the Flash Cell using Tools TSUPREM4 and MEDICI Study of HSPICE This is the first cell to be developed for the Mega cell library with the newly established 0.8-micron process in CMOS technology of SCL. This was required to accomplish the designs of ongoing and future complex systems. Pre Silicon parameter for the FLASH EEPROM will be extracted after this process development step. Then using this pre silicon parameter we are going to develop the spice model for the flash EEPROM in HSIPCE and then basic circuit design part of the Flash EEPROM will be implemented. Thus it required the study of the given architecture and its modification for improvements, optimization and characterization and its final implementation in the layout. EDA Tools from TMA were used for all simulation. Thereafter modeling of the Flash Cell was carried out. From the available characteristics of various structures a structure is selected according to optimum performance and requirement is select it for pre silicon extraction. The thesis is divided into two basic parts; Part I covers general theory of FLASH EEPROM, While Part II covers the whole design of FLASH EEPROM.