Implementation Of Remote Video Surveillance System on Cradle’s SoC

Abstract

Video processing loads have driven processors to consider a wide range of architectural approaches to deal with the sheer volume of pixel data. As the preferred medium for communication and entertainment, video resolutions and frame rates show no signs of leveling off. Processor clock speeds, while having dutifully risen per Moore’s predictions, still can’t keep up with ever increasing demands of the video marketplace. Similarly, compression algorithms, despite an order of magnitude jump in network capacities every couple years and the rapid drop in storage costs have only continued to rise in implementation complexity. This paradox has brought about a variety of architectural approaches to tackle throughputs demanded by video processing applications. However, few can scale to the unending rise in processing demands. Traditional DSP/CPU architectures increase clock rate and multiple issue rates at the rate defined by Moore’s law. But clock speedups have a limited potential as Moore’s law hits a breaking point. With that realization, several designers have begun the transition to multi-core multiprocessor architectures. Indeed, multiprocessor chips are becoming more common because of advantages of scalability of design. This project describes the implementation of remote video surveillance on cradle 3SoC. It is a complete solution for a surveillance system of national importance and first of its kind in India. It is a complete wireless system in the range of 5 kms. This project highlights the advantages of dedicated devices in the System on Chip, which helps in developing a complete real time system eradicating the need of any other external resources. A s a part of the system H.261 based video compression and G.711 based audio compression standards have been implemented on this SoC. The need of the device drivers for the serial mode of communication plays the key role for the HDLC protocol implementation.