Design, Analysis and Synthesis Of CMOS PLL

Abstract

The growing need for integration of mixed analog digital system requires the automation of analog design process ultimately leading to a complete EDA tool which can take care of design process from specifications to layout. A Phase-Locked Loop PLL) is one such essential analog building block, which has wide range of applications such as clock and data recovery in broadband communication systems, frequency synthesis in radio frequency (RF) transceivers, clock generation in microprocessors, and synchronization in TV receivers. Increase of design complexity and at the same time demand of design time reduction due to highly competitive market can be managed only by the use of computeraided design. A synthesis tool is one such automated tool using computer-aided techniques, which provides the net-list of the circuit for the given specifications of the circuit. Analog/ Mixed circuit synthesis requires detailed circuit knowledge to provide design automation; a major approach for the analog circuit synthesis has been knowledge-based approach. Hence, this approach has been chosen for the synthesis of PLL. This approach includes a detailed analysis of basic sub-blocks of the PLL and the derivation of the empirical relations between the system parameters (lock time, center frequency) and the device dimensions. In the present work, the design synthesis of three PLL architectures has been done. An operational amplifier (op-amp) is an important building block of analog circuits and basic sub-block in PLL; hence a synthesis tool has been separately developed for the op-amp. The physical design of one of the PLL architectures has also been presented.