Verification Of Soc With Ethernet - eVC

Abstract

Now a day in world of SoC and million gates complex chips, verification consumes 60-80% of the manpower on complex chip projects. So improving verification productivity is an necessity. So eInfochips has made an e Cerification Component for verification of Ethernet Protocol. This Project “Verification of Soc with Ethernet eVC” includes a number of tasks related to verification Process. Ethernet –eVC is a ready-made Verification Component to verify the Ethernet design as stand alone or as a component of a more complex system. So first step is to understand Ethernet Protocol as well as eVC, which follows the Reusable Methodology defined by Verisity. It also requires understanding of UNIX operating system, Specman Ellite – a verification environment and “e” – verification language. The second step is to verify eVC itself for its correct functionality before using it to verify any of Ethernet design. So the majority of dissertation work contains creation of Verification Environment to verify eVC, to create test scenarios, to check eVC for all intended functions, to get optimum coverage and to resolve any discrepancy if found. As the Ethernet – eVC contains nine interfaces, these tasks should be carried out for all interfaces individually. Once we finished with verification of eVC, we started verifying RTL code of Ethernet using eVC. Then we started developing verification environment for a new interface RGMII. The verification work also includes some of the tasks like to review and optimize eVC and VE code, to run regression and analyze the regression results, to solve the quarries related to eVC, and to document all the procedures and details in form of user guide format.