To Design, Verify and Implement I2C and Maxim 3-Wire Serial bus protocols” Major Project Report (Part – II)

Abstract

This thesis presents the design and implementation of I2C core and the later part verification of Maxim 3 wire core. One of the most popular synchronous interfaces is the inter-integrated circuit (I2C), which was developed by Philips in 1980s. I2C is a low-bandwidth, short-distance, two wire interfaces. The I2C interface is modest in its hardware resource requirements, because only a single pair of signal lines is needed: serial data (SDA) and serial clock (SCL). Data can be transferred at a rate of up to 100 kbps in Standard mode and up to 400 kbps in Fast. Each slave on the bus is identified by a unique address. This report presents us with implementation of I2C Master/Slave core. The concept is to provide the whole functionality of I2C bus protocol to the user, keeping interface communication with the application as simple as possible. The user interface enables the application communication with I2C bus on a parallel address. The core can be configured as master or slave as per requirement .It provides detail implementation of an I2C core on ASIC, FPGA or CPLD. In later part attempt has been made to develop verification environment for Maxim 3 wire core, which is also a serial protocol. The verification environment helps to create and executable model of specification. It provided complete functional verification to Maxim 3 wire RTL core.