Design Of An Architecture For Concatenative Speech Synthesis Application

Abstract

Verification is not a test bench, nor is it a series of test benches. Verification is a process used to demonstrate the functional correctness of a design. By saying functional correctness means the design to be verified has to adhere with some predefined rules or standard. In other words design under test should behave as per specified rules. We all perform verification processes throughout our daily lives: balancing a checkbook, tasting a simmering dish, associating landmarks with symbols on a map. These are all verification processes. T o day, in the era of multi-million gate ASICs, reusable Intellectual Property (IP), and System-on-Chip (SoC) designs, verification consumes about 70% of the design effort. Design teams, properly staffed to address the verification challenge, include engineers dedicated to verification. The number of verification engineers is usually twice the number of RTL designers. When design projects are completed, the code that implements the test benches makes up to 80% of the total volume. It is also the reason verification is currently the target of new tools and methodologies. These tools and methodologies attempt to reduce the overall verification time by enabling parallelism of effort, higher levels of abstraction and automation. Providing higher levels of abstraction enables you to work more efficiently without worrying about low-level details. e V C consists of a complete set of elements for stimulating, checking and collecting coverage information on the device under test (DUT). The eVC expedites creation of a more efficient test bench for DUT. The eVC can work with both Verilog and VHDL devices and with all HDL simulators that are supported by Specman Elite. eVC can be used as full verification environment or can be added to existing environment. The eVC interface is viewable and thus can be the basis for user extensions. This thesis report put some light on developing verification environment for the verification of Ethernet eVC (e Verification Component). Architecture of eVC has been discussed. eVC reduce verification time by atomizing the verification process. First few pages of report gives the answers of some fundamental questions like what is verification, why it is required and importance of verification. White Box approach has been used to verify eVC, and Coverage Driven Verification process used to verify functionality.