Design and Implementation Of Highly Reliable, Low Power PHY Baseband Processor Based On IEEE 802.15.4

Abstract

The project entitled “Design of an Architecture for Concatenative Speech Synthesis Application” is the work carried out as part of M.Tech Dissertation at the IC Design Group of CEERI, Pilani. The project aims at providing scalable hardware architecture for concatenative speech synthesis. Speech synthesis is the result of a particular and original imitation of the human reading capability, submitted to technological and imaginative constraints that are characteristics of the time of its creation. Concatenative speech synthesis is a method of generating speech from pre-recorded speech database. To provide a hardware solution the hardware-software co-design approach is followed, wherein the algorithms are implemented in software, and analyzed for computation and hardware requirements and then the corresponding hardware is generated at RT (Register Transfer) level by using an Hardware Description Language (like VHDL). The Unit selection approach for speech synthesis is followed, under which a low memory speech database is used, in this project concatenative speech synthesis is done by linear prediction of speech. Algorithms for linear prediction are first implemented in ‘C’, the computation and corresponding hardware required are analyzed. Hardware architectures for the problem specified are given for 32-bit floating point numbers by designing the RTL blocks for floating point arithmetic; also for the selection of speech units hardware architectures for pattern matching algorithms have been explored.