Low Voltage Low Power SRAM Design

Abstract

Memory is an essential element of today's electronics. Modern digital systems require the capability of storing and retrieving large amounts of information at high speed. According to ITRS roadmap in 2002, memory chip will occupy 90% of chip area in 2013. Static Random Access memories are mostly used as a Cache in various applications. However recent trends in SRAM Design include issues such as low power, low voltage & high-speed operations. This project is about Low power, Low voltage SRAM design. Hereby Semiconductor memories, SRAM architecture, Low voltage & Low power design, SRAM Design and Decoder design are described. The SRAM design involves design of various circuits such as Precharge Circuit, SRAM Cell Design, Bit Selection, Decoder Design, Write Circuit & Read Circuit. The SRAM is designed using 1-micron technology (2V, 100 MHz) with Tanner Tool. Using Cadence SRAM is redesigned with 0.18-micron technology (1.6 Volt, 1 GHz). Depending upon technology, supply voltage & operating frequency are chosen. At low voltage, three different SRAM Circuits- Current Mode Read- Current Mode Write, Current Mode Read- Voltage Mode Write and Voltage Mode Read- Voltage Mode Write are designed. The simulation results obtained are compared to have better performance. The specifications for SRAM design are finalized using simulations results of all three designs of SRAM & literature survey. 1 Mb of CRCW Asynchronous SRAM is designed using 0.18 um technology using Cadence tool for the low voltage operation of 1.6V. In order to achieve low power operation various techniques such as memory partioning, multi-stage decoding, Current mode read-write operation & Address Transition Detect (ATD) etc are used. The 1 Mb of SRAM is organized as 64 kb X 16 bits. Thus size of data bus is 16 bits. The SRAM is divided into 4 main blocks. These four blocks are further divided into 8 sub blocks with size of 32 kb each. The sub block of 32 kb is arranged as 256 rows X 128 Columns. To select any one row of the sub block three-stage decoder is used. The decoder is designed with 2 input Nakamura’s NAND gate. When external clock signal is V used for generating internal control signals, the circuit is turned on every cycle yet no operation is requested. Besides that, the clock cycle period might be too long for an operation to complete. As a result, asynchronous SRAM design using Address Transition Detection (ATD) circuitry is used to reduce power consumption by supplying pulse signals to the internal circuitries. The project is organized as follows: Initial five chapters describe general theory of Semiconductor Memories, SRAM, Low Voltage, Low power operation and recent trends in SRAM design. Next three SRAM designs- CRCW, VRVW & CRVW are implemented using Tanner & Cadence. Decoder design is discussed next. Finally using specifications 1 Mb of Asynchronous CRCW SRAM is implemented along with I-O, Control Circuit, ATD and multi stage Decoder. The obtained pre-layout simulation results are discussed in chapter 6 to 9. Layout & post-layout results are mentioned in chapter 10.