Interconnect Performance Estimation Techniques

Abstract

Interconnect is the physical link used for the connection of two di erent networks/circuits or to connect the network/circuit to the external devices. There are mainly Memory Inter- connect, Quick Path Interconnect (QPI) used for the connection between two processors, External peripheral controller i.e. Platform Controller Hub (PCH) for connection of low speed peripherals and Peripheral Component Interconnect Express. Memory Interconnect is one of the CPU interconnects which is used to improve the capacity and bandwidth of the link. Instead of direct link between CPU and RAM, we use MXBs (Memory Bu ers) in-between to increase the capacity and bandwidth. Signals through interconnects are subjected to degradation due to various factors like signal speed, rise time, fall time, jitter, overshoot, undershoot, ringing etc. Several tech- niques are developed to compensate these losses. Some of the techniques developed to compensate the losses are Tx equalization, Rx equalization, load resistor compensation, skew compensation and tuning/training circuits for a given platform. There are mainly two types of methods used for the performance estimation of the in- terconnect. One is Stand alone performance estimation technique and the other is on system performance estimation technique. The existing methodology takes long time for BER measurements. In this thesis we have proposed a new methodology which will help to reduce the time for the measurement of BER. The new methodology develop- ment is on the Receiver Performance Estimation. The approach is based on the Stand alone performance estimation. We have carried out tests at each timing value (i.e. by varying the delay), and we have observed signi cant reduction in time required for BER measurement.