Validation of Next Generation Intel Xeon Processor in Coverage Collection, Memory Matrix and Optimization

Please use this identifier to cite or link to this item: http://10.1.7.192:80/jspui/handle/123456789/4303

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DC Field	Value	Language
dc.contributor.author	Patel, Ronak M.	-
dc.date.accessioned	2013-12-20T07:12:36Z	-
dc.date.available	2013-12-20T07:12:36Z	-
dc.date.issued	2013-06-01	-
dc.identifier.uri	http://10.1.7.181:1900/jspui/123456789/4303	-
dc.description.abstract	Post-Silicon environment is a tremendous challenge as the design complexity is increasing with next generation processors. The aim of this project is to analyze several coverage points, collect various coverage data samples across di erent soft- ware/hardware combinations, write test cases on various memory risers and validate di erent types of combinations in memory matrix. At last, some automation in cov- erage collection and memory matrix both is also incorporated.	en_US
dc.publisher	Institute of Technology	en_US
dc.relation.ispartofseries	11MECC12	en_US
dc.subject	EC 2011	en_US
dc.subject	Project Report	en_US
dc.subject	Project Report 2011	en_US
dc.subject	EC Project Report	en_US
dc.subject	EC (Communication)	en_US
dc.subject	Communication	en_US
dc.subject	Communication 2011	en_US
dc.subject	11MECC	en_US
dc.subject	11MECC12	en_US
dc.title	Validation of Next Generation Intel Xeon Processor in Coverage Collection, Memory Matrix and Optimization	en_US
dc.type	Dissertation	en_US
Appears in Collections:	Dissertation, EC (Communication)

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