Verification Of Behavioral Models for Analog IP’s

Abstract

As process of fabrication technology advances, chip complexity increases and the design flow becomes more iterative. Iterations in the design flow cost money, time and engineering resources that adversely affect the time to market and cost of the devices being designed. Verification dominates most chip development schedules, with electronic firms pouring up to 70 percent their engineering resources into the task. Unfortunately, this high level of investment hasn’t always paid off in terms of first-silicon success. According to a recent survey, 71 percent of all IC designs fail on first silicon and require at least one re-spin. 60 percent of these faulty designs have functional errors that could have been detected with more thorough RTL verification. In subsequent years HDL simulator performance and capacity advanced significantly, but verification engineers found that additional capabilities were needed. This resulted in the emergence of numerous bolt-on tools that worked with simulation, for example,coverage analysis, assertion checking, and Test bench automation. This report deals with the development of a generic verification environment of HDL models and describes the validation process and need for automation of validation environment of Phased Locked Loop(PLL) behavioral models. The project deals with writing Test bench in Verilog to validate behavioral models and using Shell Scripts to automate the validation process. NOTE: Since the work done in this project is of confidential nature, more stress is given on concepts than on actual work done.