Architecture Evaluation for Programmable Logic (90nm/65nm)

Abstract

Pluralities of electronically reconfigurable gate array (ERCGA) logic circuits are interconnected via a reconfigurable interconnect, and electronic representations of large digital networks are converted to take temporary actual operating hardware form on the interconnected circuits. The reconfigurable interconnect permits the digital network realized on the interconnected circuits to be changed at will, making the system well suited for a variety of purposes including simulation, prototyping, and execution and computing. The reconfigurable interconnect may comprise a partial crossbar that is formed of ERCGA circuits dedicated to interconnection functions, wherein each such interconnect ERCGA is connected to at least one, but not all of the pins of a plurality of the logic circuits. Here in STMicroelectronics we divide the programmable logic in two part software and hardware. In software we work on PiCoGA and in hardware we preparing a library of 90nm and 65 nm. This report first gives some introduction of programmable logic. After that it gives brief explanation of PiCoGA. Then it covers the basic of Griffy- C the language used for the PiCoGA. Then it moves on the layout side in which it gives the implement of 90nm library with minimizes routing area. The comparison of the reduce routing are with the old version is also present Then it cover the modified base cell of 65nm and implement the 65nm library on that base cell with the comparison table. Then it covers the detail backend flow with the synthesis of given RTL code, PNR of that synthesis code with the help of developed library of 90nm/65nm. The example for the flow is also present for CRC code implementation with VHDL code and its simulation results.