Implementation of Sense Amplifier-based D Flip-Flop using 0.25 nm and 0.18 nm Technology

Abstract

The traditional Flip-flops and latches suffer from the large delays and the race conditions. This paper describes a new approach to the D flip-flpo design using the sense ampiifier. The previous efforts in the same direction made at the 0.25 am Technology exhibit improvements in clock-to-oulput delav and power dissipation with respect to recently proposed high speed Flip-flops. The paper discusses the Flip-Flop at the 0.18 pm Technology. The output latch of the of the proposed circuit can be considered' as a hybrid solution between the standard NAND-based SR latch : and the N-C2MOS approach, The present Technology exhibits improvements in clock-to-output delay and power dissipation with respect to recently proposed high-Speed flip-flops.