FPGA Based Implementation Of Hearing Aid Digital Filter

Abstract

The project entitled “FPGA Based Implementation Of Hearing Aid Digital Filter” Solution is an endeavor to help those people suffering from hearing impairment, who are unable to afford the costly digital hearing aids available in the market. This project is currently being worked upon in the INFOTECH department of CEERI ,Pilani. The present report deals with the filter designing part of the digital hearing aids. This report also deals with the study of various types of filter approximations available, and concludes with a proposed design of digital filter for the hearing aid device. From MATLAB results we found filter coefficients and for these coefficients we have implement filter in VHDL. For more accuracy after fixed point filter implementation in VHDL we have to go for floating point implementation of IIR filter. Till now I have completed Real to IEEE-754 converter in VHDL and floating point multiplier in VHDL. CEERI Pilani has therefore taken up this project, so as to replace the existing analog technology hearing aid device with the homemade digital technology ones, which will be far better in terms of performance together with reduce cost.