Design and Development of IP-Core of FET for FPGA

Abstract

The aim of this study was to investigate the different problems associated with the design and implementation of a DDR SDRAM Memory Controller. This work has lead to a working implementation of a DDR SDRAM Memory Controller that is meant to be used as a reference for future implementations. The reports highlights design issues and propose solutions to problems. The result of this study is not only applicable when designing a DDR SDRAM Memory Controller. The DDR SDRAM is an enhancement to the traditional Synchronous DRAM. It supports data transfers on both edges of each clock cycle, effectively doubling the data throughput of the memory device. The DDR SDRAM operates with a differential clock: CLK and CLK# (the crossing of CLK going High and CLK# going Low will be considered as the positive edge of the CLK). Commands (address and control signals) are registered at every CLK positive edge. Input data is registered on both edges of the DQS (data strobe), and output data is referenced to both edges of DQS, as well as to both edges of CLK. The DDR SDRAM transmits a bidirectional data strobe during reads and by the memory controller during writes. DQS is edge-aligned with data for reads, and center-aligned with data for writes.