RTL Design of DDR2 SDRAM Controller

Abstract

The project entitled “Ethernet MAC Receiver” is work carried out as a part of M.Tech Dissertation at Time To Market India Pvt. Ltd Hyderabad. The project aims to provide suitable RTL design for MAC Receiver. Here the receiver supplies receive data to the host system from the receive data stream. It detects the preamble and SFD, checks the length field, and executes CRC check. Status information on each received packet, such as the number of received bytes and occurrence of errors, is written to a register after reception has been completed. This status information can be appended to the data stream output from the receive FIFO to the host system. If status register contain in formation not favor with controller then packets can be eliminated from the receive FIFO.