Automated Generation of Timing Constraints for SoC DFx Fabric

Abstract

Timing constraints are critical during logic synthesis. False paths are unavoidable constraints while working with large SoC Fabric. Including them while performing tim- ing analysis reduces additional complexity in design, that would be required otherwise. Usually a TAP fabric contains 80 to 200 TAPs. This introduces thousands of false paths in fabric. If false paths are violating timing requirements, clock time period has to be increased and thus frequency will decrease which is not desirable. Identifying each false path currently is manual process. It takes 1-2 man months. Also it is tedious and error prone process. The proposal is to automatically generate timing constraints (false paths) for the SoC. Network connectivity information can be taken in some machine readable format (xml, rtl) and algorithm gives register to register false path as synthesis timing exception. These constraints can be given to synthesis for timing analysis. This is lots of effort saving method for timing analysis of SoC fabric. Currently idea is proposed for TAP fabric which can be further extended for whole SoC fabric.