FPGA Based System for Image Compression & Transmission

Abstract

This thesis focuses on the high level modelling and implementation of a FPGA Based System for Image Compression & Transmission using Simulink and the libraries provided by the Xilinx System Generator. The Simulink model is then mapped to a Xilinx Spartan 6 Field Programmable Gate Array (FPGA) board to serve as a co-processor of a real-time video. The use of FPGA technology enables the adaptation of hardware to various protocols and environments by software and therefore saves development time and hardware costs. Compression through FPGA is done by using system generator present in the Matlab-Simulink. The image JPEG encoder is composed of several algorithms which allow the trans-formation and compression of data. Such algorithms include Discrete Cosine Trans-form, Quantization, and Huffman Coding. The key technologies developed in this thesis are the exploration of data parallelism using reconfigurable hardware, as well as the use of fixed point arithmetic for the conservation of hardware resources.