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Title: | Verification of Communication And Interfaces IPs of Set-Top Box |
Authors: | Joshi, Chintan Arunbhai |
Keywords: | EC 2012 Project Report Project Report 2012 EC Project Report EC (Communication) Communication Communication 2012 12MECC 12MECC10 |
Issue Date: | 1-Jun-2014 |
Publisher: | Institute of Technology |
Series/Report no.: | 12MECC10; |
Abstract: | In Semiconductor Industry, the emiconductors Intellectual Property (SIP) has profound impact on the design of system on chip(SoC). SIP has become a key part of the electronic design process because it can reduce IC development costs, accelerate time-to-market, reduce time-to-volume and increase end-product value. It can provide a solution that enables companies to bridge the "design gap", Electronic design automation (EDA) tools are used to design complex Application Specific ICs (ASIC). Before manufacturing of SOCs it is necessary to verify its functionality so that bugs in the design can be removed. EDA tools Verifies the IP to find and removes bugs. As the technology progresses, every electronic device get miniaturized and more functions are added in that minimum size. the digital set-top box which are having advanced capabilities are designed. some functions of set-top box are discussed in the report. Ethernet based subsystem is there in set-top box to accommodate router in it. The Inter IC(I2C) bus and Serial Peripheral Interface(SPI) bus are inside set-top box for communication between two internal components inside the set-top box. Functional verification provides a lot of benefits to the IC designers. Testing of a large design using SoC consumes longer compilation time in case of debugging and committing small mistakes. Simulation based testing is faster and also provides capability to check all the signals buried under the design. The library and package oriented feature provide an efficient way of writing testbenches in the system verilog. The Universal Verification Methodology (UVM) Class Library provides the building blocks needed to quickly develop reusable and well-constructed verification components and test environments using SystemVerilog. In this thesis i have implemented testing environment using system Verilog and UVM for I2C controller. During the training period, verification of Ethernet based subsystem, I2C bus and SPI bus of the digital set-top box, implementation of testing environment using system Verilog and UVM for I2C controller is done during internship period. |
URI: | http://hdl.handle.net/123456789/4710 |
Appears in Collections: | Dissertation, EC (Communication) |
Files in This Item:
File | Description | Size | Format | |
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12MECC10.pdf | 12MECC10 | 1.79 MB | Adobe PDF | ![]() View/Open |
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