Low Bitrate Modulator (RTL Design) using FPGA

Abstract

All electronic communication systems have a transmitter , a communication medium and a receiver. Modulator and Demodulator are essential part of any communication system. For a long distance transmisson , modulation process is required. The process of modulation makes the information signal more compatible with the medium or channel. Modulator & Demodulator (MODEM) in satellite is one of key module. In digital communication system data speed is one of the important parameter. Data speed is related with type of modulation scheme. Bit rate and Baud rate are used to express the data speed in digital communication system. Bit rate is chosen according to applications. There are some applications which use low bit rate MODEM. Low bit rate MODEM are low cost, consumes low power and low error rate in comparison to high bit rate MODEM. The thesis covers the RTL design of Binary Phase Shift Keying Modulator and Demodulator on reconfigurable platform like FPGA. It allows to dynamically adapted depending on the noise in the communication medium.The reconfigurable FPGAs are capable of using the high density IP cores for the Filter design and communication. Here Register Transfer Level (RTL) design of BPSK Modulator & Demodulator is done using Simulink Model with help of System Generator Block Set and Xilinx Block Set.Then this MATLAB model is used as golden reference to design RTL view of BPSK Modulator & Demodulator in Xilinx FPGA . Simulation process is carried for BPSK MODEM and waveforms are veried along with golden reference. Then the RTL design and its implementation is tested on Spartan 3 deviceand MODEM is working at 1200 bps. The chip used for the design is Spartan3,xc3s400-5pq208.