Formal Equivalence Verification For Vlsi Design

Abstract

Verification of any design consumes about 70% of the total turnaround time of design process. Thus different tools and flows are been developed to reduce the time required for verification. All the inputs required for the tool are generated by the flow, a wrapper around the tool. Verification gets easily done if the flow is tool friendly and generates all the required files by tool in proper format. This report details the ways that can be used to reduce the time of verification. As a result of which the total time of design process can be reduced. Verification is done between two different designs either at same abstract level or at different abstract levels. It is observed that the run-time decreased by increasing the auto- mapping in the flow for the constraints picked by tools. All the solutions concluded by this project are applicable for functional unit block (FUB) and sub-section level FEV.