RTL To GDSII Implementation of Low Power Design

Abstract

Design (cf5x_core) Consist of Four Modules cf5x_core_in, cf5x_core_out,spp_l2_cache, cf5_core_kbus, Design is operating at 200Mhz. There is various Low power techniques available 1.Multple Supply Voltage(MSV) 2.Power Shut off (PSO) 3.Dynamic voltage frequency scaling (DVFS) CPF enabled flow is used for logic synthesis and physical implementation. Common Power Format(CPF) is use to capture the power intent for your design, a standardized format for specifying power-saving techniques early in the design process, to deliver an end-to-end low-power design solution. Low power DVFS technique is implemented. Design is divided in two power domains Pd_vddb_vss and pd_vdda_vss . power doamains are operating at the voltages. power domain pd_vddb_vss is operating at the 1.3v and its default power domain. power domain pd_vdda_vss is operating at the 1.1v and has the switched on and off capability. power domain pd_vddb_vss has module cf5_core_kbus.power domain pd_vdda_vss has module cf5x_core_in, cf5x_core_out & spp_l2_cache. Level Shifter are used for the signal that passes between power domain pd_vddb_vss and pd_vdda_vss because to up and down signal voltage level. Isolation cells are used for the signal going from pd_vdda_vss to pd_vddb_vss to pass known value to power domain pd_vddb_vss when power domain pd_vdda_vss is switched off. State Retention cells are used for sequential cells in power domain pd_vdda_vss to retain there previous state during the switched off state. Power Switches are added in the power domain pd_vdda_vss to provide switched on and off capability. Design is synthesized using CPF enabled flow.Level Shifter,Isolation and state retention cells are inserted at this stage Design is Physically Implemented using the CPF enabled flow.Power Switches are added at this stage. Physical implementation steps are 1.floorplanning 2.power planning 3.placement 3.ClockTree Synthesize 4.Routing 5.Timing analysis 6.Signal Integrity 7.Power Analysis.