Please use this identifier to cite or link to this item: http://10.1.7.192:80/jspui/handle/123456789/4727
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dc.contributor.authorSelani, Yusuf-
dc.date.accessioned2014-08-06T12:17:50Z-
dc.date.available2014-08-06T12:17:50Z-
dc.date.issued2014-06-01-
dc.identifier.urihttp://hdl.handle.net/123456789/4727-
dc.description.abstractThis Project Report explores the Analysis, Post-Layout Extraction, Set-up development, Design-validations and Cut-Generation of Single port Static Random Access Memories (SRAM) & Read only memory (ROM) with 90 nanometer three Metal layer Technology. The SRAM characterization includes various measurements like timings & capacitances. Validation includes the analysis of performance aspects of Memory Cell, Verification of functionality by applying Tight Stimuli which is generated by timing values, Marginality Analysis; Write through Analysis, Power-On Reset Analysis, Sense-Amp-Offset Analysis, Self-time Read Analysis, Self-time Write Analysis, Latch Analysis, Sense-Pulse-Width Analysis. CUT generation is done for providing the Specification of a memory cut through a Graphical User Interface on WebGen. I investigate the methodology of characterization of the parameters and validation of functionality.en_US
dc.publisherInstitute of Technologyen_US
dc.relation.ispartofseries12MECV30;-
dc.subjectEC 2012en_US
dc.subjectProject Reporten_US
dc.subjectProject Report 2012en_US
dc.subjectEC Project Reporten_US
dc.subjectEC (VLSI)en_US
dc.subjectVLSIen_US
dc.subjectVLSI 2012en_US
dc.subject12MECen_US
dc.subject12MECVen_US
dc.subject12MECV30en_US
dc.titleDesign & Analysis of SRAM Memory Compiler & its Characterisationen_US
dc.typeDissertationen_US
Appears in Collections:Dissertation, EC (VLSI)

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