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DC Field | Value | Language |
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dc.contributor.author | Selani, Yusuf | - |
dc.date.accessioned | 2014-08-06T12:17:50Z | - |
dc.date.available | 2014-08-06T12:17:50Z | - |
dc.date.issued | 2014-06-01 | - |
dc.identifier.uri | http://hdl.handle.net/123456789/4727 | - |
dc.description.abstract | This Project Report explores the Analysis, Post-Layout Extraction, Set-up development, Design-validations and Cut-Generation of Single port Static Random Access Memories (SRAM) & Read only memory (ROM) with 90 nanometer three Metal layer Technology. The SRAM characterization includes various measurements like timings & capacitances. Validation includes the analysis of performance aspects of Memory Cell, Verification of functionality by applying Tight Stimuli which is generated by timing values, Marginality Analysis; Write through Analysis, Power-On Reset Analysis, Sense-Amp-Offset Analysis, Self-time Read Analysis, Self-time Write Analysis, Latch Analysis, Sense-Pulse-Width Analysis. CUT generation is done for providing the Specification of a memory cut through a Graphical User Interface on WebGen. I investigate the methodology of characterization of the parameters and validation of functionality. | en_US |
dc.publisher | Institute of Technology | en_US |
dc.relation.ispartofseries | 12MECV30; | - |
dc.subject | EC 2012 | en_US |
dc.subject | Project Report | en_US |
dc.subject | Project Report 2012 | en_US |
dc.subject | EC Project Report | en_US |
dc.subject | EC (VLSI) | en_US |
dc.subject | VLSI | en_US |
dc.subject | VLSI 2012 | en_US |
dc.subject | 12MEC | en_US |
dc.subject | 12MECV | en_US |
dc.subject | 12MECV30 | en_US |
dc.title | Design & Analysis of SRAM Memory Compiler & its Characterisation | en_US |
dc.type | Dissertation | en_US |
Appears in Collections: | Dissertation, EC (VLSI) |
Files in This Item:
File | Description | Size | Format | |
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12MECV30.pdf | 12MECV30 | 2.09 MB | Adobe PDF | ![]() View/Open |
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