Memory Design and Performance Evaluation of Memory Compiler

Abstract

Memory design is one of the most important part of any System on Chip (SoC) design. As the technology is advanced to a nanoscale, the requirement for the fast and low power memory design is at high insist. As the leakage current (Off-current) is dominant and cannot be neglected in Deep Sub-micron Technology, the low leakage part is also essential in memory design.

In This report, The basic architecture of memory design is discussed. The two part of memory design, namely bitcell design and peripheral design is discussed. Mainly two types of memory bitcell are widely used in memory chip design, namely SRAM and DRAM. In this report, The basic 6T SRAM bitcell (Single port) and 8T bitcell (Dual port) are discussed. The critical parameter in memory design like Write Margin, Static Noise Margin (SNM) and Read Current are also discussed in this report. The various enhancement technique (Timing enhancement, power enhancement and leakage reduction) for memory design is also discussed in this report.

In the further chapters, The basic information for Memory Compiler and its Basic fea- tures are discussed. It is also explained that how the memory compiler are useful for Memory Design. At last, The checks to evaluate the performance of Memory Compiler are also discussed.