Improvement to Intel's analog Design Verification Flow for 22nm and below Design

Abstract

Design of Low Power Analog Integrated Circuits on leading edge process technologies poses a significant challenge due to a number of issues like EOS, Gate Oxide Breakdown due to excess electric field on oxide of MOS gate, Aging stress, Breakdown of Inter Layer Dielectric (ILD) or Bias Temperature Stress (BTS), and Signal Integrity to measure the quality of signal. Conventional circuit simulation using SPICE is not good enough as it has an Insufficient Coverage. Extent of analysis of a circuit simulation is only as good as the input stimulus. If stimuli are not comprehensive many pitfalls in the circuit cannot be identified. The effort is also large as circuit simulation is expensive from compute time and human effort standpoint. Due to this we often need non-conventional methods such as Static Verification. It also fails to identify the Circuit Issues Early due to its requirement of human effort to setup the simulation (writing test benches). Ideally a designer would like to identify any fatal issues in circuit as soon as schematic editing is done rather than identifying them by setting up and running circuit simulation. For long operation it is necessary to include Aging Effects which Conventional SPICE simulation cannot simulate on circuit due to Hot Carries and PBTI. Due to the above reasons, design flows include 2 critical verification steps of Static Electrical Rule Checking – that is verification of circuit for problematic / risky patterns without actually applying stimuli and Special Aging Simulation flow to analyze circuit degradation. Current static verification flow at Intel has some disadvantages due to long runtime, generation of unmanageable false violations. With the increasing frequency, signal suffer with high frequency effect due to ringing, reflection, cross talk, ground bounce. It generate the jitter in the signal. Conventional signal integrity tool is not efficient and not correlate with the actual Jitter value. The focus of the internship project is to improve the Intel’s static verification flow efficiency. Also, there are similar inefficiencies in aging verification flows as well as signal integrity verification flow. The internship work overall involves analysis of Intel’s requirements for Aging, EOS, Signal integrity and GOX robustness of circuit, developing methods to identify and mitigate them and developing and performing quality assurance of an efficient design flow.