RTL to GDS-II Implementation of VLSI Design in `nm' Technology

Abstract

As the technology sizes of semiconductor devices continue to decrease, the effect like congestion, signal integrity, crosstalk etc. are becoming more significant on nanometer technologies. These all factors are affecting and forcing various technological methodologies throughout the design flow to constantly fight and keep updating the EDA tools to cop-up with these issues.

Physical design flow consists of producing a production-worthy layout from a gate-level netlist subject to a set of constraints. This report focuses on the steps involved in the physical design flow, problems imposed by shrinking process technologies, and the methods used to tackle these problems.The aim of this project is to successfully complete ASIC design flow from RTL to GDS-II, using the advance industry level tools. This project provides a solid base and practical hands-on experience of advanced tools like Cadence Encounter Digital Implementation System (Physical implementation for high-performance, giga-scale, low-power, and mixed-signal designs at advanced and mainstream process nodes),which gives complete solution for Logic Synthesis, Floor planning, Power Network Synthesis, Placement, Clock Tree Synthesis and Routing. Along with this, the analysis of various design factors affecting the performance of the final chip such as power, area and timing is also performed. Power analysis performed by Apache RedHawk tool & timing signoff is done by Synopsys Primetime.

Using these advanced tools the ultimate goal of the project is achieving timing closure means design free from Logical violations, Physical violations (Connectivity-opens, shorts), Design Rule violations (min spacing, min width, min via enclosure) & meeting the timing specifications (setup & hold timings).