Challenges In Subsystem Verification

Abstract

The project deals with the verification environment present in a system on chip design. The project is the part of the Intel’s IP Subsystem based project which aims to integrate various IP’s to a main Intel processor to achieve a smart and power efficient design. The key goal of this project is to perform UART and UART BFM verification and quality improvement of UART BFM. Along with this improve the UART functional coverage and code coverage. The project also includes planning for test plan review and finding holes along with Test bench or case review. The functionality of UART and its BFM is validated through the various test cases written in C and hardware languages like system Verilog and OVM (Open Verification Methodology) along with the simulation results. Writing of assertions to check the UART protocol and analyzed the assertions.