Optimization in IO Characterization Methodology

Abstract

The ever-increasing competition in the semiconductor industry requires the developers to reduce the design-to-market time of their products continuously. Along with adding more advanced features in the products, it is also important to take care that the development process is fast, and the accuracy maintained. Automation of various processes is thus imperative in saving time and helping designers expedite their design flow. Today, the I/O structures require the greatest amount of circuit design expertise along with detailed process knowledge. It is the I/O element which finally interfaces the core signal to the off chip environment. Thus however efficient the core design may be, it is the I/Os which determine the efficiency of the chip. It is very important to ensure that the designed I/O is functional and works well within the specifications & after fabrication. Due to the Scaling of CMOS Technology ,the number of Corners for characterization has increased abruptly. Characterization is validations of Physical Design over variation of all the parameters viz. Process, Temperature, Supply Voltages, Slope & Capacitive Load also known as PVTSC, each PVTSC is a unique corner. Characterization mainly involves leakage power, internal energy and timing constraints (setup, hold, recovery, removal, pulse width). Thus characterization task is vast and expanding hence methodology of doing it need to be fast, optimized and automatized, in order to reduce Design-to-Market time. The optimization in Characterization Methodology can be done by using novel statistical techniques.These statistical techniques help to fasten the task by avoid ELDO simulations as much as possible, as ELDO simulation bottle-neck the speed of Characterization. By Statistical Techniques the Characterization results can be achieved much faster then simulation Physical Design over all the PVTs with a mild trade-off of accuracy with huge gain in less Design-to-Market time.