Design and Verification of DDR IP Memory Controller

Abstract

The aim of this study is to investigate the different problems associated with the design and implementation of a DDR3 SDRAM Controller with standard interfaces AXI and AHB for data and register access respectively. In industry one of the biggest challenges is to verify such complex IPs and even if the IP is pre verified then also the SoC teams need to verify the IP. In order to facilitate reuse of verification infrastructure the standard testbench methodology, Accellera Universal Verification Methodology (UVM) is used. This methodology is supported by all the major simulator vendors like Synopsys, Cadence and Mentor Graphics. The study also focuses on how to partition such big designs and makes the design parameterized, so that various different implementations can be tried out. The data paths and control paths are implemented as separate blocks. The design provides several hooks for future enhancements and commercialization. The report highlights design issues and proposes solutions to problems like data resynchronization and how to phase shift the data strobe.