Physical Design Of Function Unit Block Using Random Logic Synthesis Methodology

Abstract

Server Chip is demanded more as the large use of social networking and the numbers of users are increases day by day. Intel is still covers 90% segment of the server chip market. I wrote this the with the experience of working with good server chip design team at Intel. The project on which I worked is a very high server SoC chip which is designed using 14nm technology. This thesis is focused on the method which is used for backend design. The word physical design refers to the conversion of RTL code (Which is coded in Hardware Description Language to implement some functionality) in to Graphic Database System (GDS) format file (Which is used for manufacturing process) by satisfying several constraints like area, power, speed and performance. However these are different ways for this purpose, but the demand to implement most of the functionality in a single chip increases the complexity and hence an efficient method to design such complex chip is required. RLS (Random Logic Synthesis) is one of the techniques which are very much useful for such a complex design. The competition in the market is huge and so TTM (Time To Market) plays an important role for winning the market, so to meet this TTM and produce the chip in very effective way there is a specific synthesis approach which Intel follows. And this method is a key part of that process. RLS flow includes logic synthesis, physical synthesis, timing analysis, timing optimization, FEV (Formal Equivalence verification), noise analysis and manufacturability (DRC/DFM) ready. In the design of high speed microprocessor, meeting the timing requirement is critical. Timing has to meet both setup as well as hold time for the design in GHz frequency space. Later Formal Equivalence Verification is done on the post-synthesis, post physical-synthesis and routed database with RTL to check the formal equivalence. The main responsibility of RLS team is to synthesize the code given by RTL owners to physical level by reducing the setup and hold violations that are produced during the various stages. This is project report is mainly focus on the basic RLS design flow and some techniques use for each steps of the flow to meet the constraints of the design. I have tried to include the more about the limitation and more advantages of this methodology in this thesis.