Functional veri cation of Memory controller for LPDDR of 333 MHz using UVM

Abstract

The Design under Verification called MCB (Memory Controller Block) is a dedicated embedded multi-port memory controller that simplifies the task of interfacing the FPGA devices to the most popular memory standards. It uses the DMC (Dynamic Memory Controller) core of ARM to enhance the features and to come up with the higher performance IP with reduced power consumption. Verification of an IP requires multiple step approach where basic features tests, random tests, error tests need to be developed along with 100% functional and code coverage. In such approach re-usability and ability to configure a verification component plays a vital role. To address such challenge various verification methodologies are available, one of the latest and most advanced one is Universal Verification Methodology (UVM). Using UVM, highly flexible verification components such as Stimulus Driver, DUT output Monitor, Tests Sequences along with supporting base sequences, Transaction Classes and Scoreboard are developed. Besides UVM infrastructure, various System Verilog based components are required for complete and robust verification. The SV based components consists of Functional Coverage and Assertion. To speed up the environment development and find out the bugs at an initial stage bring up VIPs of widely used protocols are integrated, in MCB verification AXI VIP is plugged-in. Assertions are also developed to monitor the activity as it is also the most important part of verification.