Physical Implementation Of Asic Design And Flow Optimization

Abstract

Physical implementation is gateway of an ASIC design to physical/real world. It is mainly driven by PPA (Power, Performance and Area) targets. Design is implemented using EDA tools with pre-defined constraints and targets. This implementation is divided in various small but significant steps like, synthesis, floorplanning, placement, power planning, clock tree synthesis, routing, etc. The flow starts with the RTL or Verilog files of the design and gives a GDS-II database for the same as final outcome. GDS-II database of ASIC design is sent for fabrication once physical implementation achieves PPA targets with given constraints. This thesis covers the physical implementation of Memory Management Unit (MMU). As it is a configurable design, multiple configurations of MMU are implemented to ensure achievement of PPA targets and the same are discussed in detail. Primary goal of implementation trials is to push PPA numbers. Several modifications and improvements that are done on the native implementation flow to achieve and improve PPA numbers for the design are also discussed. Several Clock Tree Synthesis experiments, their results and recommendation from that are mentioned in this document. Implementation trials of design over couple of foundry platforms and across couple of implementation nodes are also discussed here. Basic information about physical implementation flow is also provided. Descriptions related to EDA tools given here are based on implementation of design on cadence EDA tools, RTL Compiler for synthesis and Encounter Digital Implementation for rest of the flow.