IRNSS Navigation Processing and User Interface for Different Platforms

Abstract

A GPS receiver based on FPGA and MicroBlaze was developed[4].SAC, ISRO also developed same kind of receiver based of its satellite IRNSS-A. This kind of GPS receiver is made up of a RF Front-End and FPGA, with and Xilinx Kintex board. The RF Front-End receives the IRNSS signal and converts it to IF signal which is transferred to FPGA .The correlators array, C/A code generator, C/A code DCO and carrier DCO were analyzed and designed with Verilog hardware description language on FPGA[4][6].The algorithm of acquisition and tracking of GPS signal were discussed and implemented with MicroBlaze soft processor core. Meanwhile, the MicroBlaze soft processor core is responsible for communicating with FPGA user logic via the interface. In Xilinx Kintex board soft core is used that works quite slowly than hardware. To avoid performance issue Xilinx ZYNQ board is be used. It contains FPGA and two Cortex A9 arm processor on board. Here the entire requirements to implement a IRNSS receiver are on hardware so performance and e_ciency is increased. Xlinix ZYNQ board is compact in size and highly powerful than earlier design of a Microblaze and FPGA.