Ethernet GMAC IP Verification

Abstract

The aim of the Subsystem verification in High Speed Interfaces group is to focus on the integration of subsystem and to verify SYNOPSYS Controller for different functionality so that the SOC becomes bug free. Further, the subsystem goes into SoC and SoC verification is performed to assess that the IP is correctly integrated at the top level and formerly developed tests shall be instrumental in achieving the objective . The hard processor system (HPS) provides two Ethernet media access controller (GMAC) peripherals. Each GMAC can be used to transmit and receive data at 10/100/1000 Mbps over Ethernet connections in compliance with the IEEE 802.3 with specification. The GMACs are instances of the Synopsys DesignWare. Universal 10/100/1000 Ethernet GMAC (DWC-gmac) RGMII(Reduced Gigabit Medium Independent Interface).The aim is also to verify the different functionality of Ethernet GMAC is : Energy Efficient Ethernet(IEEE802.3az), MTL(MAC Transaction layer) MAC-PHY interconnect, Time stamping (IEEE 1588-2008), Frame Filtering, Checksum offload Engine, Power Management Block etc. We have used constraint random verification technology to verify the subsystem to find maximum bugs in a system and resolve it. For the Subsystem Verification the LVP(Lightweight Virtual platform) and VAL(Verification Abstraction layer) based verification environment is used . LVP is SystemC TLM based Light Weight virtual platform used in Subsystem Verification. The intent of the platform is to provide a preliminary platform with minimum required components which permits to run test software and permits to plug the RTL IP, corresponding verification IP and facilitates the RTL IP verification. LVP is based on ARM Cortex R4 processor. A SystemC wrapper around the Cortex R4 Fast Model ISS is created with Transaction Accurate Channel (TAC).The virtual platform could be used as a subsystem in the verification environment. A verilog wrapper is provided of the virtual platform and various master/slave interfaces are exposed to be integrated with IP components or verification IP components.

The Verification IP is reusable verification module consists of Bus functional Model, traffic generators, protocol monitors, and functional coverage blocks. verification IP accelerates the development of a complete verification environment to cut down the time to test the IP. Our Subsystem Verification for the SOC helps to make the SOC bug free and it also fulfils customers need for different functionality in Ethernet GMAC to be verified and working without errors.