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DC Field | Value | Language |
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dc.contributor.author | Soni, Rajanikant | - |
dc.contributor.author | Amin, Gireeja | - |
dc.contributor.author | Devashrayee, N. M. | - |
dc.contributor.author | Mehta, Usha | - |
dc.date.accessioned | 2014-12-09T09:07:21Z | - |
dc.date.available | 2014-12-09T09:07:21Z | - |
dc.date.issued | 2012-04 | - |
dc.identifier.issn | 0974-3596 | - |
dc.identifier.uri | http://hdl.handle.net/123456789/5234 | - |
dc.description | International Journal Of Computer Applications In Engineering, Technology And Sciences (IJ-CA-ETS), Vol. 4 (2), April -September, 2012, Page No. 200 - 204 | en_US |
dc.description.abstract | This paper presents a study on a digitally calibrated DAC, based on a strictly R-2R topology with operational amplifier which is able to derive high resolution - high performance DACs, in terms of INL and DNL. It has been proven by simulations that the performance of the conventional R-2R DAC can be optimized, regardless of resistors tolerance and the DAC resolution. | en_US |
dc.relation.ispartofseries | ITFEC006-9; | - |
dc.subject | Digital To Analog Conversion | en_US |
dc.subject | Resolution | en_US |
dc.subject | Linearity | en_US |
dc.subject | INL | en_US |
dc.subject | DNL | en_US |
dc.subject | Glitch | en_US |
dc.subject | EC Faculty Paper | en_US |
dc.subject | Faculty Paper | en_US |
dc.subject | ITFEC006 | en_US |
dc.subject | ITFEC010 | en_US |
dc.title | Design Simulation And Characterisation Of Op-Amp Based 3 Bit R-2r Segmented Dacs | en_US |
dc.type | Faculty Papers | en_US |
Appears in Collections: | Faculty Papers, EC |
Files in This Item:
File | Description | Size | Format | |
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ITFEC006-9.pdf | ITFEC006-9 | 151.8 kB | Adobe PDF | ![]() View/Open |
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