Implementation Of Compaction Algorithm For ATPG Generated Partially Specified Test Data

Abstract

In this paper the ATPG is implemented using C++. This ATPG is based on fault equivalence concept in which the number of faults gets reduced before compaction method. This ATPG uses the line justification and error propagation to find the test vectors for reduced fault set with the aid of controllability and observability. Single stuck at fault model is considered. The programs are developed for fault equivalence method, controllability Observability, for automatic test pattern generation and test data compaction using object oriented language C++. ISCAS 85 C17 circuit is used for analysis purpose. Standard ISCAS (International Symposium on Circuits And Systems) netlist format is used. The flow charts and results for various ISCAS 85 C17 circuits are given in this paper. The test vectors generated by the ATPG further compacted to reduce the test vectors data. The algorithm is developed for the test vector compaction and discussed along with results.