Implementation of SOBEL Edge Detector on FPGA Using System Generator

Abstract

Edge detection serves as a pre-processing step for many image processing algorithms such as image enhancement, image segmentation, tracking and image/video coding and one of the key stages in image processing and object recognition. This edge detection algorithm is based on MATLAB simulation and FPGA implementation. With the introduction of reconfigurable platform such as Field Programmable Gate Arrays (FPGA) and advent of new high level tools to configure them, image processing on FPGA has emerged as a practical solutions for most of computer vision and image processing problems. The design utilizes powerful design tool System Generator (Sys Gen) and Xilinx Development Kit for hardware-software code sign. Currently the image processing algorithms has been limited to software implementation which is slower due to the limited processor speed. So a dedicated processor for edge detection and segmentation is required which was not possible until advancement in VLSI technology. Now more complex system can be integrated on a single chip providing a platform to process real time algorithms on hardware. To meet the speed and area constraints, it is important to quantify the reduction in processing speed as well as FPGA resources that can be achieved if a component of the image/video processing system is embedded onto a hardware based platform like an FPGA. A flexible field programmable gate array device lets develop the image processing application so that the same logic substrate is reconfigured and reused by several custom coprocessors during the different operation stages of the sequential biometric algorithm. The results obtained with this technology reveal that a reconfigurable FPGA faces both real-time and parallel compute-intensive demands of the image enhancement process. This paper outlines, an efficient FPGA based architecture for Edge Detection using Sobel operator and uses Thresholding method for Segmentation. Sobel edge detection algorithm results in significantly reduced memory requirements decreased latency and increased throughput with no loss in edge detection performance and its property of less deterioration in high levels of noise.