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dc.contributor.authorThaakar, Ujjwal-
dc.contributor.authorUpadhyay, Darshana-
dc.date.accessioned2015-07-10T05:31:06Z-
dc.date.available2015-07-10T05:31:06Z-
dc.date.issued2014-03-
dc.identifier.issn0973-7391-
dc.identifier.urihttp://hdl.handle.net/123456789/5504-
dc.descriptionIJCSC, Vol. 5 (1), March - September, 2014, Page No. 101 - 102en_US
dc.description.abstractConversion of binary representation into BCD is a very frequently used operation in modern computers due to the exponential increase in the demand for decimal arithmetic. Decimal data processing applications have developed exponentially in recent years thus increasing the need to have hardware support for decimal arithmetic. Most conversion algorithms are fixed bit. we propose an algorithm that is generic and independent of the size of the binary word to be converted.A general purpose algorithm can greatly simplify and unify the process of building BCD conversion hardware implementations at a certain performance cost. This paper illustrates a generic algorithm for converting any n-bit number to its packed BCD equivalent. It is based on an insight into the relationship between a number and its BCD representation. This paper presents novel high speed low power architecture for n- bit binary to BCD conversion.en_US
dc.publisherIJCSCen_US
dc.relation.ispartofseriesITFIT012-3;-
dc.subjectAlgorithmen_US
dc.subjectBCDen_US
dc.subjectBinaryen_US
dc.subjectConversionen_US
dc.subjectGenericen_US
dc.subjectComputer Faculty Paperen_US
dc.subjectFaculty Paperen_US
dc.subjectITFIT012en_US
dc.titleRapid and Compact Generic binary-to-BCD Conversion Circuit for Less Powerful Computational Devicesen_US
dc.typeFaculty Papersen_US
Appears in Collections:Faculty Papers, CE

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