Hardware Implementation of Greatest Common Divisor using subtractor in Euclid Algorithm

Abstract

This paper proposed an efficient implementation of digital circuit based on the Euclidean Algorithm with modular arithmetic to find Greatest Common Divisor (GCD) of two Binary Numbers given as input to the circuit. Output of the circuit is the GCD of the given inputs. In this paper subtraction-based narrative defined by Euclid is described, the remainder calculation replaced by repeated subtraction. The selection of the Division Method using subtractor is due to ease of implementation and less complexity in connection with reduced hardware. The circuit is built using basic digital electronic components like Multiplexers & comparator (A<B) as control function and Registers, Full subtractor as Register transfer components. Although the circuit is developed to handle 4-bit of data, it can be easily extended to handle any number of bits just by increasing capacity of basic components (Multiplexer, Registers, Full Subtractor and comparator).