Repeater Optimization Methodologies for Custom CPU Designs

Abstract

In VLSI circuits, delay and power dissipation are the two major design constraints. The millions of devices in active state and interconnects connecting a large number of devices on chip are responsible for these problems. The repeaters are inserted in long interconnects in the VLSI circuits to reduce delay. Repeater insertion is done for the timing optimization of interconnects. But the use of repeater implies a significant cost in power and area. Repeaters consume a large part of the chip resources (area and power). Thus, there is a need of area and power optimization of the interconnect with repeaters in high speed VLSI circuits. The work carried out discusses area and power optimization of repeaters inserted in interconnects in the CPU Designs without violating the timing constraints. The proposed methodology aims to come with a flow which does the Repeaters Optimization which is aware of the Timing Margins as well as it gives area and leakage reduction, thus saving both area and power in the design without violating the timing requirements. This repeaters optimization methodology has been implemented for different PVT (Process-Voltage-Temperature) corners : single corner as well as multi-corner (nominal and highv) to converge the timing for the two design corners after optimizing the repeaters. Repeaters are used to repeat long interconnects to sustain the slopes according to project targets. Extractions as well as interconnect delay calculation tools support this well-established methodology. Simulator tool has is used to optimize these repeaters. However, running Repeater optimization flow using Simulator to downsize the repeater or swap to Low-leakage cells may cause timing miscorrelation between different PVT corners that is Nominal and High-Voltage corners. This is due to the fact that the Simulator optimization flow works on user provided timing specs that are generally generated using single corner (Nominal) data alone. This approach would have worked well in the previous generation of projects where High-Voltage convergence was not much of an issue, but in the current technologies (very low scaled down technologies) where interconnect RC’s play a key role, the timing paths between the two corners can be different, depending on whether they are Gate-Capacitance dominated or whether they are RC-dominated. Due to this uniqueness of timing critical paths across corners, it is imperative that any optimization tool should consider the worst case timing margins across PVT corners. This technique suggest one of the workarounds that can be used to generate Repeater Optimization solution by considering the multi-corner worst case timing margins. The comparison of large-sized repeaters vs small-sized repeaters is done and the optimum (small-sized) repeater is used in the design. The comparison of low-leakage repeaters vs high-leakage repeaters for interconnects in the CPU design is analyzed, and the optimum repeater is used. All these optimizations are done without violating the timing constraints. The complete tool flow is automated and GUI is created for the selection of optimum repeaters used in the design. After optimizing the repeaters, there has been a significant saving in the area for the repeaters, on an average by about 15%-20% area is saved depending upon the section, margin threshold value and slope threshold value. This approach causes about three times increase in the low-leakage repeater cell's count.