USB3 Subsystem IP Verification Based On Modified Platform

Abstract

Systems-on-Chip (SoC) are one of the biggest challenges engineers have ever faced. In real time systems for accurate performance of the system, each module of system should be verified accurately and efficiently. Efficient leads to cost effective. Total verification cost consists of men hours used and cost of tools used in verification. The aim of subsystem verification is to focus on the integration of subsystem which is combination of link and physical layer and to test it for different functionalities so that it becomes bug free. Further, the subsystem goes into SoC and SoC verification is performed to assess that the IP is correctly integrated at the top level and formerly developed tests shall be instrumental in achieving the objective of SoC verification. USB3 subsystem IP represents the controller that provides USB 3.0 protocol interface. It supports On the Go functionalities and also enhanced low power link layer states. For re-usability in SoC, verification tests are developed in C language and to integrate this software in subsystem verification, platform based verification methodology is used. LVP is System C TLM based Light Weight virtual platform. The intent of LVP is to provide a preliminary platform with minimum required components which permits to run test software and permits to plug the RTL IP, corresponding verification IP and facilitates the RTL IP verification. Top layer of LVP gives interfacing ports of different protocols i.e. AMBA, STBUS etc. LVP is made with ARM Fast Model for which software should be compiled with arm cross compiler (ARMCC) to generate executable. This processor model can be replaced with System C based processor model HCE which is light as compared to ARM and do not required any license as it is open source. With HCE code can be compiled with open source compiler (GCC). Replacement of processor model leads to requirement of verification of LVP itself that qualifies that processor is generating valid transactions on the ports or not. At last, IP is verified with efficient cost and given to SoC team for integration with other IPs and reusing the formerly developed tests.