Timing And Power Co-Optimisation Based On Z Advisory Generation

Abstract

Power is gaining importance with every generation of new Processor Architecture designs as products come up in different form factors and enter into new mobile segments. In fact, for many of the current and future products, power is the top priority. In design convergence flows, if margin on a timing path is more positive than a certain threshold, the logic cells in the path are either downsized or converted to low leakage cells for power reduction. Hence, better timing margin translates into more power optimization opportunities. In general, during design cycle, focus of the designer is on meeting the timing requirements. Very few designers spend additional effort to create extra positive margin for power reduction. The work presented in this report is an advisory developed to find circuit nodes where timing improvements can lead to a larger number of cells, moving to more positive margins subsequently leading to significant power savings. Main advantage of creating such advisory is to provide a list of handful nodes with high region of interest (ROI) to the designers. After doing timing improvement as suggested by advisory, designers will be able to increase low leakage cells count by 10%. Additionally, data from this advisory can be fed back to the synthesis flows which can be tuned to achieve better positive margins for high power ROI nodes. This advisory can also be used to allocate positive timing margin between different blocks for overall optimal power gain. This advisory can be part of any circuit design flows.