Ensuring Hardware and Software Compatibility of Generic Interrupt Controller (GIC) Architecture Validation Suite (AVS)

Abstract

The Generic Interrupt Controller (GIC) is a system level architecture provided by ARM. It defines the architectural requirements for handling all interrupt sources for any processor connected to a GIC. It’s a common interrupt controller programming interface applicable to uniprocessor or multiprocessor systems. The GIC architecture validation suite (AVS) plays important role for validating GIC architecture and providing infrastructure supports for various system implementation. GIC AVS enhances the hardware and software compatibility of GIC architecture.

The hardware compatibility enhancements are mainly provided through infrastructure support for enabling and disabling various GIC functionalities like GIC bypass support, virtualization, trust zone support among others. GIC bypass allows interrupt sources to deliver interrupts directly by asserting IRQ and FIQ pins instead of delivering through GIC. It is a backward compatibility feature that allows interrupt sources to deliver interrupts as GIC is not present in system. One of the implementations wants GIC without bypass support and handle all the interrupt sources by GIC. The GIC initialization code is developed in infrastructure header files. This implementation increases the scalability of interrupts and also provides a unique way of handling all interrupt sources. The other implementation wants GIC architecture without virtualization and secure monitor supports. New configurations, call back functions and exclude lists, are implemented for supporting such implementation. All the changes for enhancing hardware compatibilities are validated successfully on simulator with more than 99% pass rate which satisfy the coverage requirement of GIC AVS.

The software compatibly tasks are mainly enhancing GIC AVS code quality, efficiency and tool chain supports. The tool chain support task is to make GIC AVS test cases compatible to open source Low Level Machine Language (LLVM) compiler tool chain along with backward compatibility to ARM proprietary tool chain. All the ARM proprietary compiler intrinsic are replaced with LLVM compatible intrinsic. The code quality task is mainly for v8R architecture based implementation as it allows warning free patch only. This task also reduce the log files size generated through regressions. The GIC AVS efficiency is improved by providing higher page table granularity. The GIC AVS previously ran with only 4K granularity. This granularity defines the size of single page entry in page table. ARM memory architecture supports multi-level address translation. Each level of translation provide location of page table located in physical memory. The number of bits translated in each level is depend on page granule size. The levels of translation is reduced as the number of bits translated in each level is more. This simply implies the advantages of higher granule page table. The 64K and 16K page table input files are created for providing higher granule support for GIC AVS. All the changes and development carried out for enhancing software compatibility are validated on simulator by gaining more than 99% pass rate which satisfy the coverage requirement of GIC AVS.