Autochecking and Correction of Placement in Physical Design

Abstract

Any digital system design is process of converting Register Transfer Logic (RTL) design to routed gate level netlist considering provided constraints and targets for timing. Implemented design also has to meet power specifications and Design Rules. After successful implementation of the design, it can be fabricated on the silicon and ICs can be made. Physical implementation of any design follows a flow which is called physical design flow or RTL to GDS-II flow. Modern digital system requirements have lots of additional complexities. There are many of components is fixed or movable blocks in the design. With this complexity, Designer is faced to finding an arrangement of peaceable objects under strict wire length, timing, and power constraints. So there is strong demand for better design and faster automation tools for higher accurate reporting. The PnR tool being used always tries to place a flop near other flops which are interacting with it. Encounter tool will automatically place combinational logic near flops which are interacting to their paths and do optimized placement. There is still some scope of optimization was present. Hence we will analyses the timing report generated by Encounter database tool, pick up worst negative genuine path and will do all check i.e. Placement check for Combinations Cells and Placement check for Flops. Modifying the placement and updating the table with every iteration check till we get the optimized results after checking the slacks of the related flops and the combinational logic present in the worst negative slack path. This work experimentally proves that there is a strong demand for optimized placement of standard cells as quality gap exists between manual placement and automatic placers.