Test Content Development for Fault Coverage of Advanced Graphics Processor

Abstract

The advancement in manufacturing technology and complexity in architecture makes chip testing tough and tedious. There can be several reasons for a chip failure such as design or fabrication flaws, environmental factors and many more. The physical defects may consist of break in line, short in interconnections and point defects. So, good quality tests are required to detect the faults that are induced during manufacturing. This project work discusses the fault grading methodology which is very crucial for developing the test vectors. Industry standards measure the product quality in terms of defects per million. It is very important to maintain the quality of the chips and be able to reject the faulty ones. This is done by running test patterns on the chip and verifying them with known results. After fabrication, the wafer is tested by Automatic Test Equipment (ATE), whose major constraints are cost and time consumption. These constraints are met by choosing only the good quality tests from the complete test suite. The process of selecting more effective tests is called fault grading. So, fault grading is a crucial step to be followed before generating the test patterns. The test patterns are generated from a set of tests. The tests should be capable enough to find a faulty chip and reject it. The quality of a test is determined by its fault coverage count. It is defined as the ratio of detected faults by a test to the total number of detectable faults. To carry out the fault grading efficiently, a fault model is built that maps the physical behavior of defects in the circuit. High fault coverage does not ensures the detectability of all the defects across the chip. Rather, it simply means that the test is able to detect most of the faults that are considered in the fault model. So, it is equally important to build an effective fault model. As a part of the project, fault grading is being done for the decoder and encoder unit of the Intel’s Graphics Processing Unit (GPU). The fault coverage numbers have been extracted using the industry standard tools. Single stuck-at fault model has been used for the fault grading methodology. The method used is modular test generation i.e. tests have been written separately for each functional block. Proposed methodology is generic enough to fault grade any block on any complex Application Specific Integrated Circuit (ASIC) or System on Chip (SoC) design.