Development of Verication IP for DSPI

Abstract

Automotive electronics are rapidly growing industry. Nowadays, automobiles are equipped with more featured embedded systems to provide attributes and functionality to the user. The Electronic Control Unit (ECU) is installed in automobiles for application such as engine control, body electronics, brake control systems, in-car entertainment, etc. The number of ECUs installed in a modern car are around 200-250. Such massive number of embedded controllers are installed in car for comfort. This all has become possible due to the advancement in semiconductor industry. As per Golden Moore rule, number or transistors implemented on die increases the complexity of the die. With the advancement in technology, multiple cores and Ips installed on a single chip constitutes SoC. The functional correctness of SoC depend on individual IP and their behavior with other peripheral IPs. Such, complexity causes issues like integrity to become dominant. For this, it is necessary to verify the complete SoC for corner case. A standard approach is required to verify IP core based SoC design. This process needs to be faster to reduce time to market. As per the riddle `necessity is the mother of invention', the verication process is also becoming more modern. To verify circuit on the breadboard to UVM, where it is possible to automate the process of verication and generation of stimuli has made much dierence. In addition to that, Universal Verication Methodology (UVM) class library provides fully reusable, pre-veried, plug play component based on System Verilog. The work embodied in this thesis presents Development of Verication IP for DSPI controller using UVM. The verication IP is developed and included in Testbench structure as well as testcases are developed to verify DSPI IP at SoC level.