Analog Io Test-Chip Validation (PRE & Post – Silicon Validation)

Abstract

I/O’s are placed on the periphery of the chip. Any I/P signal which comes from off chip environment into the chip, must be checked by I/O for any discrepancy in its behaviour other than defined by the core for that particular signal. IO’s acts as protection device for core, scans the signal going from core to off-chip modifies any deteriorated signal detected into suitable signal for proper functioning of chip. In the following thesis analog IO test - chip validation is divided in two phases. In that phase I mainly focus on pre - silicon validation and phase II focus on post - silicon validation. In phase I i.e. pre - silicon validation in which a library consists of different cells like Bi-Directional Cell, Analog Cell, Supply Cell, Filler Cell etc. Test chip is designed for validating all the Electrical specification of the cells provided in the user manual. In this dissertation, a new approach of designing a test-chip is developed using a JTAG block. By using JTAG well be able to integrate more number of libraries on a single test-chip. This approach will be helpful in saving a lot of silicon area ie. a lot of cost saving will be there in the silicon industry. Conventional method of designing an I/O test-chip and their validation methods have also been discussed. These test-chips are at different technology node as M55, 28nm FDSOI, 45nm technology. Some designs of IO cell have also been analyzed. Integrated Circuit development cycle involves a variety of sequential stages which are equally essential to its successful completion. Post-Silicon Validation is one such process which is aimed at verification of the ICs performance at silicon level. Before shipping the device to customer it is important for test engineers to validate these Intellectual Properties (IPs) to meet the design specifications across Process, Voltage and Temperature range. Here we deal with Silicon Validation of Analog IPs such as Voltage Regulators.